1. Field of the Invention
The present invention generally relates to systems and methods for tuning wafer inspection recipes using precise defect locations.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Many different types of inspection systems have adjustable output acquisition (e.g., data, signal, and/or image acquisition) and sensitivity (or defect detection) parameters such that different parameters can be used to detect different defects or avoid sources of unwanted (nuisance) events. Although an inspection system that has adjustable output acquisition and sensitivity parameters presents significant advantages to a semiconductor device manufacturer, these inspection systems are essentially useless if the incorrect output acquisition and sensitivity parameters are used for an inspection process. In addition, since the defects, process conditions, and noise on wafers may vary dramatically (and since the characteristics of the wafers themselves may vary dramatically), the best output acquisition and sensitivity parameters for detecting the defects on a particular wafer may be difficult, if not impossible, to predict. Therefore, although using the correct output acquisition and sensitivity parameters will have a dramatic effect on the results of inspection, it is conceivable that many inspection processes are currently being performed with incorrect or non-optimized output acquisition and sensitivity parameters.
Current methods for tuning an optical inspection recipe include: (1) running a “hot” scan (i.e., one with a relatively high sensitivity (low detection threshold)), reviewing a sample (subset) of defects from the results of the inspection using a scanning electron microscope (SEM) review tool and using these defect locations to tune the recipe; or (2) obtaining images of defects from some other source such as a SEM and manually locating the defects on the wafer using various techniques and then tuning the recipe to detect those defects.
There are, however, some disadvantages of the currently used methods described above. For example, method (1) is a hit-or-miss approach based on the sample selected for SEM review. Several iterations are often needed to find suitable defects for recipe tuning since a vast majority of the “defects” detected by the sensitive recipe are nuisances (false alarms). In addition, method (2) is manual and substantially slow since it involves a human operator looking at each defect manually, and often involves destructive methods such as using “SEM burn” marks around the defect to locate it on the optical inspector.
Accordingly, it would be advantageous to develop systems and methods for determining one or more parameters of a wafer inspection process that do not have one or more of the disadvantages described above.